Generally, the functional test of sample ICs is performed as follows; various test signals are applied to each sample IC from an IC tester in each basic (test) cycle and each of the various response signals from the sample IC is fetched into the IC tester, then subjected to a defect/non-defect determination at the determination timing related to each of the response signals, thereby determining whether or not the IC functions normally.
On the other hand, along with the speedup of the operations of those ICs in recent years, the test performance of LSI testers used to test those ICs come to depend significantly on an accuracy of the timing at which the test waveform is generated. Especially, a very high timing accuracy is required at timing edges generated by a pulse generation circuit provided in such the LSI tester.
FIG. 16 shows a schematic block diagram of a conventional pulse generation circuit.
In FIG. 16, the pulse generation circuit 1 is mainly configured by a data calculation circuit 5; a pulse formation circuit 6; and a pulse delay circuit 7. The data calculation circuit 5 calculates delay value data 9 used to determine a pulse generation timing according to test pattern data 3 being sent from a pattern generation circuit (not shown) synchronously with an operation clock 4-1 and outputs the result to the pulse formation circuit 6 and the pulse delay circuit 7 respectively. Each of the pulse formation circuit 6 and the pulse delay circuit 7 generates pulses at specified timings according to the delay value data 9 (TC, D, A), each having a delay resolution (delay unit) different from others.
Next, the controlling operation of the pulse formation circuit 6 will be described with reference to FIG. 17. FIG. 20 shows the operation timing of each circuit block shown in FIG. 17. In FIG. 20, it is premised that a description related to the pulse formation circuit 6 is made, when the master clock 2 is 500 MHz (2 ns cycle) and the operation clock 4-1 is 250 MHz (4 ns cycle).
At first, the pulse formation circuit 6 generates pulses according to the delay value data (TC) 9-1 being sent from the data calculation circuit 5. As the delay value data 9-1 (TC) is sent synchronously with the operation clock 4-1, the pulse generation (delay) resolution of the pulse formation circuit 6 serves as the operation clock cycle (4 ns cycle in this example).
Furthermore, the pulse formation circuit 6, which uses the master clock 2 of which cycle is a half of the operation clock, can delay a half of the operation clock (=master clock cycle: 2 ns in this example) about pulses as the delay resolution. In FIG. 17, in the pulse formation circuit 6, the delay value data (D) 9-2 is latched to FFd 11 synchronously with the master clock. When the delay value data (D) 9-2 denotes “0”, output pulses of FFcmp 10 outputs to the FF1 (14) side. When the data (D) 9-2 denotes “1”, output pulses of FFcmp 10 outputs to the FF2 (15) side. Each of the FF1 (14) and the FF2 (15) latches received pulses. The FF2 (15) then outputs the latched pulses to the FF2′ (16) of the next stage. In other words, when the delay value data (D) 9-2 denotes “1”, the output pulses come to pass one more flip-flop circuit 16 operated synchronously with the master clock 2 than the delay path in response to “0” denoted by the data (D) 9-2. Therefore, the output pulses of the FF2′ (16) can delay just by a cycle of the master clock for the output pulses of the FF1 (14).
On the other hand, in the pulse formation circuit 6 shown in FIG. 17, the output pulses of the FF1 (14) and the FF2′ (16), generated by the operation clock 4-1, is latched to the FFor 18 through an OR gate 17 of the next stage and ANDed by the output pulses of the FFor 18 and the inverted value outputted from the FFs, which is latched once at the negative edge of the master clock 2 so as to output as inner pulses 6-1 which pulse width is shaped.
On the other hand, the pulse delay circuit 7 can delay pulses generated from the pulse formation circuit 6 by a delay resolution according to the delay value data (A) 9-3. The delay resolution is equal to or less than a half of the operation clock.
Next, the operation of the pulse delay circuit 7 will be described with reference to FIG. 18.
The pulse delay circuit 7 is mainly configured by a delay circuit 30; an FIFO 31 for reading asynchronous delay value data (A) 9-3 synchronously with output pulses 6-1; and a read FF 32.
At first, the delay value data (A) 9-3 is written in the FIFO 31 synchronously with the operation clock 4-1 and stored there. The written delay value data (A) 9-3 is read from the FIFO 31 at a timing of the trailing of the output pulse 7-1 preceding just by one pulse that has passed the pulse delay circuit 7, then inputted to the delay circuit 30.
The delay circuit 30, as shown in FIG. 19, is configured by a delay element group 34 composed of inverters, etc.; and a selection circuit 33 used to select pulse paths. In the delay circuit 30, a target path passing the pulse is selected by the selection circuit 33 according to the delay value data (A) 9-3, thereby a pulse delay value is determined.
In FIG. 19, when the delay value data denotes “1”, the inputted inner pulse 6-1 passes a longer delay time path that includes the delay element group 34 (delay value: Ans). When the delay value data denotes “0”, the inputted inner pulse 6-1 passes a shorter delay time path that does not include the delay element group 34.
As described above, the pulse generation circuit 1 can combine a digital delay time in the pulse formation circuit 6 with an analog delay time in the pulse delay circuit 7 to generate pulses at a desired timing.
This is why the pulse generation circuit 1 is often used for such waveform formation apparatus as pulse generation circuit, as well as for LSI tester, etc. Especially, in such the LSI tester, the pulse generation circuit 1 is required for generating pulses with very high accuracy, since the test performance significantly depends the waveform generation accuracy.